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19-0046; Rev. 1; 3/94
Dual, Serial-Input, Voltage-Output, 12-Bit MDAC
_______________General Description
The MAX532 is a complete, dual, serial-input, 12-bit multiplying digital-to-analog converter (MDAC) with output amplifiers. No external user trims are required to achieve full specified performance. The MAX532's 3wire serial interface minimizes the number of package pins, so it uses less board space than parallel-interface parts. The interface is SPITM, QSPITM and MicrowireTM compatible. A serial output, DOUT, allows cascading of two or more MAX532s and read-back of the data written to the device. The device's serial interface minimizes digital-noise feedthrough from its logic pins to its analog outputs. Serial interfacing also simplifies opto-coupler-isolated or transformer-isolated applications. The MAX532 is specified with 12V to 15V power supplies. All logic inputs are TTL and CMOS compatible. It comes in space-saving 16-pin DIP and wide SO packages.
____________________________Features
o Two 12-Bit MDACs with Output Amplifiers o Fast, 6MHz 3-Wire Interface o SPI, QSPI, and Microwire Compatible o 12V Output Swing o 10mA Output Current o 2.5s Settling Time to 1/2LSB o Guaranteed Monotonic Over Temperature o Low Integral Nonlinearity: 1/2LSB Max o Low Gain Tempco: 2ppm/C o Operates from 12V to 15V Supplies o Power-On Reset o Available in 16-Pin DIP and Wide SO Packages
MAX532
________________________Applications
Automatic Test Equipment Arbitrary Waveform Generators Programmable-Gain Amplifiers Motion Control Systems Servo Controls
______________Ordering Information
PART MAX532ACPE MAX532BCPE MAX532ACWE MAX532BCWE MAX532BC/D TEMP. RANGE PIN-PACKAGE 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 16 Plastic DIP 16 Plastic DIP 16 Wide SO 16 Wide SO Dice* ERROR (LSBs) 1/2 1 1/2 1 1
________________Functional Diagram
VDD
Ordering Information continued on last page. * Contact factory for dice specifications.
MAX532
VREFA
__________________Pin Configuration
DACA LATCH DACA RFBA VOUTA RFBA AGNDA VREFA 24-BIT SHIFT REGISTER DOUT RFBB VOUTA AGNDA AGNDB VOUTB 1 2 3 4 5 6 16 V DD 15 LDAC 14 CS
TOP VIEW
DIN SCLK
MAX532
13 DIN 12 DOUT 11 SCLK 10 DGND 9 V SS
CS DACB LDAC VREFB DACB LATCH VOUTB AGNDB
VREFB 7 RFBB 8
VSS
DGND
DIP/Wide SO
TMMicrowire is a trademark of National Semiconductor Corp. SPI and QSPI are trademarks of Motorola, Inc. ________________________________________________________________ Maxim Integrated Products 1
Call toll free 1-800-998-8800 for free samples or literature.
Dual, Serial-Input, Voltage-Output, 12-Bit MDAC MAX532
ABSOLUTE MAXIMUM RATINGS
Pin Voltages VDD to DGND, AGNDA, AGNDB........................-0.3V to +17V VSS to DGND, AGNDA, AGNDB (Note 1) ..........+0.3V to -17V VREFA, VREFB.............................(VSS - 0.3V) to (VDD + 0.3V) AGNDA, AGNDB .....................(DGND - 0.3V) to (VDD + 0.3V) VOUTA, VOUTB ...........................(VSS - 0.3V) to (VDD + 0.3V) RFBA, RFBB.................................(VSS - 0.3V) to (VDD + 0.3V) SCLK, DIN, DOUT, LDAC, CS ..(DGND - 0.3V) to (VDD + 0.3V) DOUT Sink Current .............................................................20mA Continuous Power Dissipation (TA = +70C) Plastic DIP (derate 10.53mW/C above +70C) ..........842mW Wide SO (derate 9.52mW/C above +70C)................762mW CERDIP (derate 10.00mW/C above +70C) ...............800mW Operating Temperature Ranges: MAX532_C__ ......................................................0C to +70C MAX532_E__....................................................-40C to +85C MAX532_MJE ................................................-55C to +125C Junction Temperatures: MAX532_C__, E__........................................................+150C MAX532_MJE...............................................................+175C Storage Temperature Range ........................... -65C to +160C Lead Temperature (soldering, 10sec) ........................... +300C
Note 1: If VSS is open-circuited with VDD and either AGND applied, the VSS pin will float positive, exceeding the Absolute Maximum Ratings. A Schottky diode connected between VSS and GND ensures the maximum ratings will not be exceeded.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V DD = 11.4V to 16.5V, VSS = -11.4V to -16.5V, AGNDA = AGNDB = DGND = 0V, VREFA and VREFB = +10V, RL = 2k, CL = 100pF, VOUT_ connected to RFB_, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER Resolution Relative Accuracy Differential Nonlinearity Zero-Code Offset Error Zero-Code Offset Temperature Coefficient INL Guaranteed monotonic TA = +25C, MAX532_ DAC latch loaded with all 0s DAC latch loaded with all 0s TA = +25C, DAC latch loaded with all 1s Gain Error TA = TMIN to TMAX, DAC latch loaded with all 1s Gain-Error Temperature Coefficient REFERENCE INPUTS (VREFA, VREFB) VREFA, VREFB Input Resistance VREFA, VREFB Input Resistance Matching 8 10 0.5 13 3.0 k % MAX532A MAX532B MAX532A MAX532B 2 TA = TMIN to TMAX, MAX532A TA = TMIN to TMAX, MAX532B 5 2 5 4 7 ppm/C of FSR LSB MAX532A MAX532B SYMBOL CONDITIONS MIN 12 1/2 1 1 2 3 4 V/C mV TYP MAX UNITS Bits LSB LSB
STATIC PERFORMANCE (Note 1)
2
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Dual, Serial-Input, Voltage-Output, 12-Bit MDAC
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 11.4V to 16.5V, VSS = -11.4V to -16.5V, AGNDA = AGNDB = DGND = 0V, VREFA and VREFB = +10V, RL = 2k, CL = 100pF, VOUT_ connected to RFB_, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN 2.4 0.8 Digital inputs at 0V or VDD 1 8 ISINK = 5mA ISINK = 16mA VDOUT = 0V to VDD 0.08 0.2 10 15 0.4 TYP MAX UNITS V V A pF DIGITAL INPUTS (SCLK, DIN, LDAC, CS) VINH Input High Voltage Input Low Voltage Input Current Input Capacitance (Note 2) DIGITAL OUTPUT (DOUT) (Note 3) Output Voltage Low Output High Leakage Output High Capacitance (Note 2) VOL ILKG COUT VINL
MAX532
V A pF
ANALOG OUTPUTS (VOUTA, VOUTB) DC Output Impedance Short-Circuit Current VOUTA, VOUTB connected to AGNDA, AGNDB Output Voltage Swing POWER REQUIREMENTS Positive Supply Voltage Negative Supply Voltage
0.2 20 (VDD - 2.5) to (VSS + 2.5)
mA V
VDD VSS Full scale/VDD, VDD = 11.4V to 16.5V, VREF = -8.9V, DAC latches loaded with all 1s
11.4 -11.4
16.5 -16.5 0.035
V V
Power-Supply Rejection
PSR Full scale/VSS, VSS = -11.4V to -16.5V, VREF = 8.9V, DAC latches loaded with all 1s 0.035 5 4 10 6
LSB/%
Positive Supply Current Negative Supply Current AC CHARACTERISTICS Voltage-Output Settling Time Slew Rate Digital-to-Analog Glitch Impulse
IDD ISS
Output unloaded Output unloaded
mA mA
Settling time to within 1/2 LSB of final DAC value; DAC latch alternately loaded with all 0s and all 1s
2.5 8
s V/s nV-s
DAC latch alternately loaded with 011...11 and 100...00 VREFA = 20Vp-p 10kHz sine wave; DAC latches loaded with all 0s VREFB = 20Vp-p 10kHz sine wave; DAC latches loaded with all 0s
60
VREFA to VOUTB Channel-to-Channel Isolation VREFB to VOUTA
-100 dB -100
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3
Dual, Serial-Input, Voltage-Output, 12-Bit MDAC MAX532
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 11.4V to 16.5V, VSS = -11.4V to -16.5V, AGNDA = AGNDB = DGND = 0V, VREFA and VREFB = +10V, RL = 2k, CL = 100pF, VOUT_ connected to RFB_, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER Multiplying Feedthrough Error Unity-Gain Small-Signal Bandwidth Full-Power Bandwidth SYMBOL CONDITIONS VREF = 20Vp-p 10kHz sine wave; DAC latch loaded with all 0s VREF = 100mVp-p sine wave; DAC latch loaded with all 1s VREF = 20Vp-p sine wave; DAC latch loaded with all 1s THD VREF = 6VRMS, 1kHz sine wave; DAC latch loaded with all 1s CS = 1; transitions on SCLK, LDAC, DIN DACA code all 1s, DACB code transition from all 0s to all 1s 0.1Hz to 10Hz MIN TYP -77 MAX UNITS dB
1.0
MHz
125
kHz
Total Harmonic Distortion Digital Feedthrough Digital Crosstalk Output Noise Voltage
-90 1.1 10 2
dB nV-s nV-s VRMS
Note 1: Static performance tested at VDD = +15V, VSS = -15V. Performance over supplies guaranteed by PSR test. Note 2: Guaranteed by design. Not subject to production testing. Note 3: Open-drain output.
TIMING CHARACTERISTICS
(VDD = 11.4V to 16.5V, VSS = -11.4V to -16.5V, AGNDA = AGNDB = DGND = 0V) (Notes 4, 5) PARAMETER SCLK Clock Frequency SCLK Pulse Width High SCLK Pulse Width Low DIN to SCLK Rise Setup Time DIN to SCLK Rise Hold Time CS Fall to SCLK Rise Setup Time CS Rise to SCLK Rise Setup Time SCLK Fall to CS Fall Hold Time SCLK Rise to CS Rise Hold Time CS Pulse Width High SCLK Fall to DOUT Valid (Note 6) CS Fall to DOUT Enable (Note 7) CS Rise to DOUT Disable (Note 7) LDAC Pulse Width Low CS Rise to LDAC Fall Setup Time SYMBOL fCLK tCH tCL tDS tDH tCSS0 tCSS1 tCSH0 tCSH1 tCSW tDO tDV tTR tLDAC tLDACS CL = 20pF, RPULL-UP = 1k to 5V CL = 20pF, RPULL-UP = 1k to 5V CL = 20pF, RPULL-UP = 1k to 5V 60 100 80 80 50 0 50 50 5 80 120 0 200 100 60 CONDITIONS MIN TYP MAX 6.25 UNITS MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note 4: All input signals are specified with tR = tF 5ns. Logic input swing is 0V to 5V. Note 5: See Figure 1. Note 6: Timing is for SCLK fall to DOUT fall to 0.8V, or for SCLK fall to DOUT rise to 2.4V. Additional time must be added for any larger passive RC pull-up delay. Note 7: DOUT enable: DOUT falls to 4.5V from 5.0V. DOUT disable: DOUT rises to 0.5V from 0V.
4
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Dual, Serial-Input, Voltage-Output, 12-Bit MDAC
__________________________________________Typical Operating Characteristics
(VDD = 15V, VSS = -15V, RL = 2k, CL = 100pF, unless otherwise noted.)
OUTPUT VOLTAGE SWING vs. RESISTIVE LOAD
25 NOISE SPECTRAL DENSITY (nV Hz) VREF = 20Vp-p at 1kHz 20 VOUT (Vp-p) 300 VREF = 0V DAC CODE = 11...111 GAIN = -1 GAIN (dB)
MAX532
NOISE SPECTRAL DENSITY
5 0 -5 -10 200 -15 -20 -25 -30 -35 0 -40 10 100 1k FREQUENCY (Hz) 10k 100k
LARGE-SIGNAL FREQUENCY RESPONSE
15
VREF = 20Vp-p DAC CODE = 11...111 GAIN = -1
10
100
5
0 10 100 1k 10k LOAD RESISTANCE ()
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
SMALL-SIGNAL FREQUENCY RESPONSE
5 0 ATTENUATION (dB) -5 GAIN (dB) -10 -15 -20 -25 100 1k 10k 100k 1M 10M FREQUENCY (Hz) -35 -40 -45 -50 -55 -60 -65 -70 -75 -80 -85 1k VREF = 100mVp-p DAC CODE = 11...111
MULTIPLYING FEEDTHROUGH ERROR
-94 VREFA = 20Vp-p VREFB = AGNDB DAC CODE = 00...00 THD (dB) -96 -98 -100 -102 -104 -106 10k 100k 1M
TOTAL HARMONIC DISTORTION + NOISE vs. FREQUENCY (BANDWIDTH = 80kHz)
VREF = 6VRMS DAC CODE = 111...111
100
1k FREQUENCY (Hz)
10k
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION + NOISE vs. FREQUENCY (BANDWIDTH > 500kHz)
-60 -65 -70 THD (dB) -75 -80 -85 -90 -95 -100 100 1k 10k 100k FREQUENCY (Hz) VREF = 6VRMS DAC CODE = 111...111
_________________________________________________________________________________________________
5
Dual, Serial-Input, Voltage-Output, 12-Bit MDAC MAX532
____________________________Typical Operating Characteristics (continued)
(VDD = 15V, VSS = -15V, RL = 2k, CL = 100pF, unless otherwise noted.) SMALL-SIGNAL PULSE RESPONSE LARGE-SIGNAL PULSE RESPONSE
AGNDA
A
AGNDA
A
A = VOUTA, 50mV/div TIMEBASE = 2s/div VREFA = 100mV SQUARE WAVE
A = VOUTA, 5V/div TIMEBASE = 2s/div VREFA = 10V SQUARE WAVE
______________________________________________________________Pin Description
PIN NAME RFBA VREFA VOUTA AGNDA AGNDB VOUTB VREFB RFBB VSS DGND SCLK DOUT DIN CS LDAC VDD Feedback Resistor for DACA Reference Input for DACA Voltage Output for DACA Analog Ground for DACA Analog Ground for DACB Voltage Output for DACB Reference Input for DACB Feedback Resistor for DACB Negative Supply Voltage Digital Ground Serial Clock Input Serial Data Output. Open-drain N-channel MOSFET output: requires external pull-up resistor. Data on DOUT changes on the falling edge of SCLK. Serial output data is delayed 24 clock cycles from DIN. Serial Data Input. CMOS- and TTL-compatible input. Data is clocked into DIN on the rising edge of SCLK. CS must be low for data to be clocked in. Chip-Select Input, active low. Data is shifted in and out when CS is low. DAC latches are updated when CS is high and LDAC is low. Asynchronous Load DAC Input, active low. DAC latches are updated when CS is high and LDAC is low. Positive Supply Voltage FUNCTION
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 6
_______________________________________________________________________________________
Dual, Serial-Input, Voltage-Output, 12-Bit MDAC
____________________________________________________________Timing Diagrams
MAX532
tCSW tCSH1 CS tCSHO SCLK tDS DIN tDV DOUT Q0 D0 tD0 Q1 Q23 D0 tDH D1 D23 tTR tLDACS
tCSSO
tCH
tCL
tCSS1
LDAC tLDAC
DACS UPDATED
Figure 1. Timing Diagram
_______________________________________________________________________________________
7
Dual, Serial-Input, Voltage-Output, 12-Bit MDAC MAX532
_______________________________________________Timing Diagrams (continued)
CS DACS UPDATED SCLK
DIN D23............................................D16 MSB DACB DOUT Q23 Q22..................................... Q16 MSB DACB FROM PREVIOUS WRITE Q15 Q14 Q13 Q12 Q11.......... MSB DACA FROM PREVIOUS WRITE Q1 Q0 D23 D23 D15 D14 D13 D12 D11.......... LSB DACB MSB DACA D1 D0 LSB DACA
Figure 2. 3-Wire Interface Timing Diagram (LDAC = DGND)
CS
SCLK
DIN D23............................................D16 MSB DACB DOUT Q23 Q22 ................................... Q16 MSB DACB FROM PREVIOUS WRITE LDAC Q15 Q14 Q13 Q12 Q11.......... MSB DACA FROM PREVIOUS WRITE Q1 Q0 D23 D23 D15 D14 D13 D12 D11.......... LSB DACB MSB DACA D1 D0 LSB DACA
DACS UPDATED
Figure 3. 4-Wire Inferface Timing Diagam
8
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Dual, Serial-Input, Voltage-Output, 12-Bit MDAC MAX532
5V 1k SCLK SK DOUT 5V
1k MISO SS
DIN
SO
DIN
MOSI
MAX532
DOUT
SI
MICROWIRE PORT
MAX532
SCLK
SCK
SPI PORT
CS
I/O
CS
I/O
LDAC
I/O
LDAC
I/O CPOL = 0, CPHA = 0
THE DOUT-SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX532, BUT MAY BE USED FOR READ-BACK PURPOSES.
THE DOUT-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX532, BUT MAY BE USED FOR READ-BACK PURPOSES.
Figure 4. Connections for Microwire
Figure 5. Connections for SPI
_______________Detailed Description
Digital Interface
The MAX532 is Microwire and SPI compatible (Figures 4 and 5). Both DACs are programmed by writing three 8-bit words (see Figures 2 and 3, and the Functional Diagram). Serial data is clocked into the data registers MSB first, with DACB information preceding DACA information. Data is clocked in on the rising edge of SCLK while CS is low. With CS high, data can not be clocked into DIN, and DOUT is high impedance. SCLK can be driven at rates up to 6.25MHz. The MAX532 uses either a 3-wire or a 4-wire serial interface. Three wires may be used (CS, DIN, SCLK) by tying LDAC low. With LDAC low, the DACs are updated simultaneously when CS goes high (see Figure 2 and the Functional Diagram). The 3-wire interface may be used if the MAX532 is used alone, or if two or more MAX532s are cascaded (DOUT of one device tied to DIN of the other) (Figure 6). The 4-wire interface (LDAC, CS, DIN, SCLK) is required if several serial devices are tied to the same data line, and it is desirable to update them simultaneously (Figure 7). With the 4-wire interface, the DACs are updated when LDAC goes low (see Figure 3 and the Functional Diagram). A serial output, DOUT, allows cascading of two or more MAX532s and allows read-back of the data written to
the device's 24-bit shift register. The data at DOUT is delayed 24 clock cycles from the data at DIN (see Figures 2 and 3, and the Functional Diagram). DOUT is an open-drain N-channel MOSFET that requires an external pull-up resistor (typically 1k if pulled up to +5V, and 3k if pulled up to +12V or +15V). Logic levels are guaranteed with sink currents up to 5mA (see Electrical Characteristics). Output data changes on the falling edge of SCLK when CS is low. If CS is high, DOUT is three-state (high-impedance).
Daisy-Chaining Devices
Any number of MAX532s can be daisy-chained by connecting the DOUT pin of one device (with a pull-up resistor) to the DIN pin of the following device in the chain (Figure 6). When daisy-chaining devices, tCSS0 (CS low to SCLK high), must be the greater of tDV + tDS or tDS + (tRC + tTR - tCS), where tCSW is the CS pulse width used in the system and the term (tRC + tTR - tCSW) accounts for the time spent charging the DOUT capacitance with the external pull-up resistor. So, for tRC < 250ns, tCSS0 is simply tDV + tDS. Calculate tRC using the following equation: tRC = RP x C x ln (VPULL-UP/(VPULL-UP - 2.4V)) where VPULL-UP is the voltage that the pull-up resistor is connected to, RP is the value of the pull-up resistor, and C is the capacitance at DOUT. Values of tRC are given in Table 1.
9
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Dual, Serial-Input, Voltage-Output, 12-Bit MDAC MAX532
+5V +5V +5V
RP 1k
RP 1k
RP 1k
MAX532
SCLK DIN CS SCLK DIN CS LDAC DOUT SCLK DIN CS
MAX532
SCLK DOUT DIN CS LDAC
MAX532
DOUT
LDAC TO OTHER SERIAL DEVICES
MAX532
SCLK DIN CS SCLK DIN CS LDAC
Figure 6. Daisy-chained or individual MAX532s are simultaneously updated by bringing CS high when using the 3-wire interface (LDAC = DGND).
DIN SCLK LDAC CS1 CS2 CS3 TO OTHER SERIAL DEVICES
CS LDAC SCLK DIN
CS LDAC
CS LDAC
MAX532
MAX532
SCLK DIN
MAX532
SCLK DIN
Figure 7. Multiple devices sharing a common DIN line may be simultaneously updated by bringing LDAC low. CS1, CS2, CS3, . . ., are driven separately, thus controlling which data are written to devices 1, 2, 3, . . . .
10
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Dual, Serial-Input, Voltage-Output, 12-Bit MDAC
Table 1. tRC Delay Times
VPULL-UP (V) 4.5 4.5 4.5 4.5 4.5 11.4 11.4 11.4 11.4 11.4 13.5 13.5 13.5 13.5 13.5 C (pF) 20 35 50 100 150 20 35 50 100 150 20 35 50 100 150 RP (k) 1 1 1 1 1 3 3 3 3 3 3 3 3 3 3 tRC (ns) 15 27 38 76 114 14 25 35 71 106 12 21 29 59 88
+12V to +15V VDD
Digital-to-Analog Section
Figure 8 shows a simplified circuit diagram for one of the DACs and the output amplifier. A segmented scheme is used to improve linearity, whereby the two MSBs of the 12-bit data word are decoded to drive the three switches, SA, SB, and SC. The remaining ten bits drive the switches S0 through S9 in a standard R-2R ladder configuration. Each of the switches, SA, SB, and SC, steers 1/4 of the total reference current with the remaining 1/4 passing through the R-2R section. The output amplifier and feedback resistor perform the current-to-voltage conversion, giving the following: VOUT_ = -D x VREF_, where _ denotes A or B, and D is the fractional representation of the digital word. (D can be set from 0 to 4095/4096.)
MAX532
With the values of tRC given in Table 1, tCSS0 is always given by tDV + tDS. For different values of R or C, tRC must be calculated to determine tCSS0. Additionally, the maximum clock frequency is limited to fCLK (max) = 1 -------------------------- . 2 x (tDO + tRC -15ns + tDS)
RFBA
VIN
VREFA
DACA
VOUTA
VOUT
DGND
VSS -12V to -15V
AGNDA
MAX532
For example, with tRC = 15ns (5V 10% supply with 1k pull-up), the maximum clock frequency is 2MHz.
VREF_ R R
Figure 9. Unipolar Binary Operation
R
2R SC
2R SB
2R SA
2R S9
2R S8
2R S0
2R
R/2
RFB_
VOUT_
SHOWN FOR ALL 1s ON DAC
AGND_
Figure 8. Simplified D/A Circuit Diagram
______________________________________________________________________________________ 11
Dual, Serial-Input, Voltage-Output, 12-Bit MDAC MAX532
Output Amplifiers
The output amplifiers are stable with any combination of resistive loads 2k and capacitive loads 100pF. They are internally compensated, and settle to 0.01% FSR (1/2LSB) in 2.5s.
__________Applications Information
Layout, Grounding, and Bypassing
For best system performance, use printed circuit boards with separate analog and digital ground planes. Wirewrap boards are not recommended. The two ground planes should be tied together at the low-impedance power-supply source, as shown in Figure 11. The board layout should ensure that digital and analog signal lines are kept separate from each other as much as possible. Do not run analog and digital lines parallel to one another. The output amplifiers are sensitive to high-frequency noise in the VDD and V SS power supplies. Bypass these supplies to the analog ground plane with 0.1F and 10F bypass capacitors. Minimize capacitor lead lengths for best noise rejection.
Unipolar Configuration
Figure 9 shows DACA connected for unipolar binary operation. Similar connections apply for DACB. When VIN is an AC signal, the circuit performs two-quadrant multiplication. Table 2 shows the codes for this circuit.
Bipolar Operation
Figure 10 shows the MAX532 connected for bipolar operation. The coding is offset binary, as shown in Table 3. When VIN is an AC signal, the circuit performs four-quadrant multiplication. To maintain gain error specifications, resistors R1, R2, and R3 should be ratiomatched to 0.01%.
Table 2. Unipolar Code Table
DAC Latch Contents MSB LSB Analog Output, VOUT -VIN x (4095/4096) -VIN x (2048/4096) = -1/2VIN -VIN x (1/4096) 0V
Table 3. Bipolar Code Table
DAC Latch Contents MSB LSB Analog Output, VOUT +VIN x (2047/2048) +VIN x (1/2048) 0V -VIN x (1/2048) -VIN + (2048/2048) = -VIN
1111 1111 1111 1000 0000 0000 0000 0000 0001 0000 0000 0000 1LSB = VIN/4096
1111 1111 1111 1000 0000 0001 1000 0000 0000 0111 1111 1111 0000 0000 0000 1LSB = VIN/2048
R1 20k +12V to +15V VDD VIN VREF_ DAC_ R3 10k
R2 20k VOUT
+15V -15V
ANALOG SUPPLY AGND
DIGITAL SUPPLY +5V DGND
RFB_ VOUT_
MAX532
DGND AGND_ VSS -12V to -15V
VDD
VSS
AGNDA
AGNDB
DGND
+5V
DGND
MAX532
DIGITAL CIRCUITRY
Figure 10. Bipolar Operation
Figure 11. Power-Supply Grounding
12
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Dual, Serial-Input, Voltage-Output, 12-Bit MDAC
Programmable-Gain Amplifier (PGA)
The DAC/amplifier combination, along with access to the feedback resistors, makes the MAX532 ideal as a programmable-gain amplifier. In this application, the DAC functions as a programmable resistor in the feedback loop. This type of configuration is shown in Figure 12, and is suitable for AC gain control. The DAC code controls the gain for the PGA. As the code decreases, the effective DAC resistance increases, and so the gain also increases. The transfer function is given by: VOUT/VIN = -REQA/RFBA, where RFBA is the value of the feedback resistor (R/2), and REQA is the effective DAC resistance controlled by the digital input code: R 4096 REQA = ---- (--------) , 2 CODE
Figure 12. Programmable-Gain Amplifer
MAX532
MAX532
R 2 VIN 1 RFBA R/2
DACA 4096 CODE
VREFA
2
VOUTA 3
VOUT
AGNDA 4 VOUT VIN = -4096 CODE
where CODE is the DAC code in decimal. The transfer function is thus: VOUT ------ = VIN -4096 ------ CODE
The code may be programmed between 1 and (212 -1). The zero code is not allowed, as it results in an openloop amplifier response.
Power-On Reset
On power-up, the internal DAC latches are set to 00 . . . . .00.
______________________________________________________________________________________
13
Dual, Serial-Input, Voltage-Output, 12-Bit MDAC MAX532
__Ordering Information (continued)
PART MAX532AEPE MAX532BEPE MAX532AEWE MAX532BEWE MAX532AMJE MAX532BMJE TEMP. RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C -55C to +125C -55C to +125C PIN-PACKAGE 16 Plastic DIP 16 Plastic DIP 16 Wide SO 16 Wide SO 16 CERDIP** 16 CERDIP** ERROR (LSBs) 1/2 1 1/2 1 1/2 1
AGNDA
___________________Chip Topography
VREFA RFBA V DD LDAC
CS VOUTA DIN
**Contact factory for availability and processing to MIL-STD-883B.
0.250" (6.35mm)
AGNDB
DOUT VOUTB SCLK
VREFB
RFBB
V SS V SS DGND
0.140" (3.56mm)
TRANSISTOR COUNT: 1324; SUBSTRATE CONNECTED TO VDD.
14
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Dual, Serial-Input, Voltage-Output, 12-Bit MDAC
________________________________________________________Package Information
D1
DIM A A1 A2 A3 B B1 C D D1 E E1 e eA eB L INCHES MAX MIN 0.200 - - 0.015 0.150 0.125 0.080 0.055 0.022 0.016 0.065 0.050 0.012 0.008 0.765 0.745 0.030 0.005 0.325 0.300 0.280 0.240 0.100 BSC 0.300 BSC 0.400 - 0.150 0.115 15 0 MILLIMETERS MIN MAX - 5.08 0.38 - 3.18 3.81 1.40 2.03 0.41 0.56 1.27 1.65 0.20 0.30 18.92 19.43 0.13 0.76 7.62 8.26 6.10 7.11 2.54 BSC 7.62 BSC - 10.16 2.92 3.81 0 15
21-587A
MAX532
E D A3 A A2 E1
L A1 e B
C B1 eA eB
16-PIN PLASTIC DUAL-IN-LINE PACKAGE
DIM A A1 B C D E e H h L
E
H
INCHES MAX MIN 0.104 0.093 0.012 0.004 0.019 0.014 0.013 0.009 0.413 0.398 0.299 0.291 0.050 BSC 0.419 0.394 0.030 0.010 0.050 0.016 8 0
MILLIMETERS MIN MAX 2.35 2.65 0.10 0.30 0.35 0.49 0.23 0.32 10.10 10.50 7.40 7.60 1.27 BSC 10.00 10.65 0.25 0.75 0.40 1.27 0 8
21-589B
D A e B
0.127mm 0.004in.
h x 45
A1
C
L
16-PIN PLASTIC SMALL-OUTLINE (WIDE) PACKAGE
15
______________________________________________________________________________________
Dual, Serial-Input, Voltage-Output, 12-Bit MDAC MAX532
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16
____________________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
Printed USA is a registered trademark of Maxim Integrated Products.
(c) 1994 Maxim Integrated Products

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